公开(公告)号：US20170099151A1

公开(公告)日：2017-04-06

申请号：US15212343

申请日：2016-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KITAK KIM ,  JI-SU KANG ,  KISEOK BAE ,  JONGHOON SHIN ,  KYOUNGMOON AHN ,  JINSU HYUN

IPC: H04L9/32 ,  H04L9/06 ,  H04W12/04 ,  H04W12/06 ,  H04L9/14 ,  H04L9/30 ,  H04L29/06

CPC classification number: H04L9/3263 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/30 ,  H04L9/3234 ,  H04L9/3271 ,  H04L63/0823 ,  H04L2209/80 ,  H04W12/06

Abstract: An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge. A shared memory stores the parsed certificate, the random number, the challenge, and the response. An authentication controller controls the certificate handler, the cryptographic primitives, and the shared memory through a register setting, according to an authentication protocol.

公开(公告)号：US20230141786A1

公开(公告)日：2023-05-11

申请号：US17859870

申请日：2022-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOHYUN SON ,  KISEOK BAE

IPC: G01R31/3185 ,  G01R31/3193 ,  G01R31/317

CPC classification number: G01R31/318597 ,  G01R31/31935 ,  G01R31/31719 ,  G01R31/31727

Abstract: A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.