公开(公告)号：US20210167040A1

公开(公告)日：2021-06-03

申请号：US16906051

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SE-HO YOU ,  KYUNG SUK OH ,  SUNKYOUNG SEO

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.

公开(公告)号：US20200075551A1

公开(公告)日：2020-03-05

申请号：US16385363

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNG SUK OH ,  DO-HYUN KIM ,  SUNWON KANG

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.

公开(公告)号：US20230096170A1

公开(公告)日：2023-03-30

申请号：US17734700

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEHWAN KIM ,  YOUNG-DEUK KIM ,  JAE CHOON KIM ,  KYUNG SUK OH ,  EUNGCHANG LEE

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

公开(公告)号：US20210057388A1

公开(公告)日：2021-02-25

申请号：US17094267

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNG SUK OH ,  DO-HYUN KIM ,  SUNWON KANG

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.

公开(公告)号：US20250054917A1

公开(公告)日：2025-02-13

申请号：US18933642

申请日：2024-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNSEOK SONG ,  KYUNG SUK OH

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538

Abstract: A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.

公开(公告)号：US20220139879A1

公开(公告)日：2022-05-05

申请号：US17325907

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： WANSOO PARK ,  SANG SUB SONG ,  KYUNG SUK OH

IPC: H01L25/065

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

公开(公告)号：US20220059505A1

公开(公告)日：2022-02-24

申请号：US17229974

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNSEOK SONG ,  KYUNG SUK OH

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.