公开(公告)号：US20240321673A1

公开(公告)日：2024-09-26

申请号：US18379286

申请日：2023-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggu KANG ,  JAE CHOON KIM ,  SUNG-HO Mun ,  Hwanjoo Park

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution layer structure, a semiconductor structure on the redistribution layer structure, at least one heat dissipation structure on the semiconductor structure, where the at least one heat dissipation structure may include a first epoxy molding compound, a molding material for molding the semiconductor structure and the at least one heat dissipation structure, on the redistribution layer structure, where the molding material may include a second epoxy molding compound, where the first epoxy molding compound may have higher thermal conductivity than the second epoxy molding compound.

公开(公告)号：US20230096170A1

公开(公告)日：2023-03-30

申请号：US17734700

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEHWAN KIM ,  YOUNG-DEUK KIM ,  JAE CHOON KIM ,  KYUNG SUK OH ,  EUNGCHANG LEE

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

公开(公告)号：US20240072020A1

公开(公告)日：2024-02-29

申请号：US18188627

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE CHOON KIM ,  Hwanjoo PARK ,  Sunggu KANG ,  SUNG-HO MUN

IPC: H01L25/10 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H10B80/00 ,  H01L23/3157 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/08112 ,  H01L2224/16227 ,  H01L2224/48221 ,  H01L2924/1436 ,  H01L2924/1432 ,  H01L2225/1058

Abstract: A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.

公开(公告)号：US20190287877A1

公开(公告)日：2019-09-19

申请号：US16139526

申请日：2018-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE CHOON KIM ,  YOUNG-DEUK KIM ,  YOUNGHOON HYUN

IPC: H01L23/367 ,  H01L23/00 ,  H01L29/41

Abstract: A heat radiation device includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A second electrode is disposed on the semiconductor substrate and is spaced apart from the first electrode. A first through electrode is disposed in the semiconductor substrate. The first through electrode is electrically connected to the first electrode.

公开(公告)号：US20180301443A1

公开(公告)日：2018-10-18

申请号：US15786698

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JICHUL KIM ,  CHAJEA JO ,  SANG-UK HAN ,  KYOUNG SOON CHO ,  JAE CHOON KIM ,  WOOHYUN PARK

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US20240321669A1

公开(公告)日：2024-09-26

申请号：US18380854

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu Kang ,  JAE CHOON KIM ,  SUNG-HO MUN ,  Hwanjoo Park

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32245

Abstract: A semiconductor package includes a substrate, a semiconductor die on the substrate, a heat spreader covering the semiconductor die. The heat spreader includes an upper plate portion, a base portion, and a sidewall portion connecting the upper plate portion to the base portion. The upper plate portion and the sidewall portion define an underlying cavity. The base portion is disposed on the substrate, extends from an exterior side of the sidewall portion in a horizontal direction, includes a plurality of first through holes, has a bottom surface at the same level as a bottom surface of the sidewall portion, and has a height in a vertical direction from a lowermost portion to an uppermost portion thereof less than or equal to that of the sidewall portion.

公开(公告)号：US20210202462A1

公开(公告)日：2021-07-01

申请号：US17204225

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JICHUL KIM ,  CHAJEA JO ,  SANG-UK HAN ,  KYOUNG SOON CHO ,  JAE CHOON KIM ,  WOOHYUN PARK

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US20200335480A1

公开(公告)日：2020-10-22

申请号：US16724592

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEEJUNG HWANG ,  JAE CHOON KIM ,  YUN SEOK CHOI

IPC: H01L25/065 ,  H01L23/367

Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.