公开(公告)号：US20190393239A1

公开(公告)日：2019-12-26

申请号：US16263417

申请日：2019-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-HWAN LEE ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

公开(公告)号：US20180294270A1

公开(公告)日：2018-10-11

申请号：US15815164

申请日：2017-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-HWAN LEE ,  MIN-KYUNG BAE ,  BYOUNG-TAEK KIM ,  HYE-JIN CHO ,  YONG-SEOK KIM ,  TAE-HUN KIM ,  JUN-HEE LIM

IPC: H01L27/1157 ,  H01L27/11582

Abstract: A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction. A channel structure penetrates through the stack gate structure in the first direction. The channel structure makes contact with the low hand gap layer. A charge storage structure is interposed between the stack gate structure and the channel structure. The charge storage structure is configured to selectively store charge and to provide the stored charge to a memory cell, the stack gate structure, and the channel structure.