公开(公告)号：US20150137320A1

公开(公告)日：2015-05-21

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  HUN-HYEOUNG LEAM ,  TAE-HYUN KIM ,  SEOK-WOO NAM ,  HYUN NAMKOONG ,  YONG-SEOK KIM ,  TEA-KWANG YU

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US20180294270A1

公开(公告)日：2018-10-11

申请号：US15815164

申请日：2017-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-HWAN LEE ,  MIN-KYUNG BAE ,  BYOUNG-TAEK KIM ,  HYE-JIN CHO ,  YONG-SEOK KIM ,  TAE-HUN KIM ,  JUN-HEE LIM

IPC: H01L27/1157 ,  H01L27/11582

Abstract: A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction. A channel structure penetrates through the stack gate structure in the first direction. The channel structure makes contact with the low hand gap layer. A charge storage structure is interposed between the stack gate structure and the channel structure. The charge storage structure is configured to selectively store charge and to provide the stored charge to a memory cell, the stack gate structure, and the channel structure.

公开(公告)号：US20170033225A1

公开(公告)日：2017-02-02

申请号：US15290269

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-HWAN KIM ,  HUN-HYEOUNG LEAM ,  TAE-HYUN KIM ,  SEOK-WOO NAM ,  HYUN NAMKOONG ,  YONG-SEOK KIM ,  TEA-KWANG YU

IPC: H01L29/78 ,  H01L27/115 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US20150179799A1

公开(公告)日：2015-06-25

申请号：US14635034

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  HUN-HYEOUNG LEAM ,  TAE-HYUN KIM ,  SEOK-WOO NAM ,  HYUN NAMKOONG ,  YONG-SEOK KIM ,  TEA-KWANG YU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.