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1.发明公开公开(公告)号：US20230194608A1
公开(公告)日：2023-06-22
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S. Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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公开(公告)号：US20240364797A1
公开(公告)日：2024-10-31
申请号：US18212518
申请日：2023-06-21
IPC分类号： H04L69/22
CPC分类号： H04L69/22
摘要： A method for managing packet header fields in a physical (PHY) layer includes: receiving, by a header descriptor array (HDA) of a PHY layer, a data packet and a status signal of the data packet; writing, by the HDA, a header field for the received data packet; storing, by the HDA, the written header field and the status signal of the data packet in a header field array; and fetching, by the HDA, the header field of the data packet by enabling parallel reading of a plurality of locations of the header field array, enabling transmission and re-transmission of the data packet.
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3.发明授权公开(公告)号：US11906585B2
公开(公告)日：2024-02-20
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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