-
1.发明公开公开(公告)号：US20230194608A1
公开(公告)日：2023-06-22
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S. Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
-
2.发明授权公开(公告)号：US11601116B2
公开(公告)日：2023-03-07
申请号：US17307489
申请日：2021-05-04
摘要： A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.
-
3.发明公开公开(公告)号：US20240044978A1
公开(公告)日：2024-02-08
申请号：US18219484
申请日：2023-07-07
发明人： Gunjan Mandal , Sunil Rajan , Raghavendra Molthati
IPC分类号： G01R31/317 , G01R23/20
CPC分类号： G01R31/31727 , G01R31/3171 , G01R23/20
摘要： Methods and systems for determining and calibrating non-linearity in a phase interpolator. Embodiments determine a first jitter value that causes the bit error rate (BER) of a data sequence to exceed a predefined target BER, when a recovered clock is aligned with the data sequence at a first PI code. The recovered clock is obtained from a data pattern representing the data sequence. Embodiments determine a second jitter value that causes the BER of the data sequence to exceed the predefined target BER at a second PI code. The first PI code may immediately precede or succeed the second PI code. Embodiments determine a Differential Non-Linearity (DNL) corresponding to the second PI code, based on a phase shift introduced to the recovered clock by the second PI code relative to the first PI code, the first jitter value, and the second jitter value. All DNL values corresponding to all PI codes may be determined in a similar manner. An Integral Non-Linearity (INL) may be determined by integrating the DNL corresponding to all PI codes.
-
公开(公告)号：US11469746B2
公开(公告)日：2022-10-11
申请号：US17352516
申请日：2021-06-21
发明人： Vishnu Kalyanamahadevi Gopalan Jawarlal , Gunjan Mandal , Avneesh Singh Verma , Sanjeeb Kumar Ghosh
摘要： An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.
-
5.发明授权公开(公告)号：US11906585B2
公开(公告)日：2024-02-20
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
-
公开(公告)号：US20220231676A1
公开(公告)日：2022-07-21
申请号：US17352516
申请日：2021-06-21
发明人： Vishnu Kalyanamahadevi Gopalan Jawarlal , Gunjan Mandal , Avneesh Singh Verma , Sanjeeb Kumar Ghosh
摘要： An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.015 秒)
