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1.发明公开公开(公告)号：US20230194608A1
公开(公告)日：2023-06-22
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S. Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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2.发明授权公开(公告)号：US11477057B1
公开(公告)日：2022-10-18
申请号：US17405514
申请日：2021-08-18
IPC分类号： H04L25/03
摘要： Accordingly embodiments herein disclose a quarter rate speculative DFE. The quarter rate speculative DFE includes a plurality of sampler circuits connected to an input terminal. The plurality of sampler circuits are configured to sample an input signal into a plurality of data samples in parallel. A plurality of quarter rate look ahead circuit connected to the plurality of sampler circuits. The plurality of quarter rate look ahead circuit is configured to simultaneously perform an align operation and a look ahead operation on the plurality of data samples based on the different clock phases to obtain a plurality of latched outputs. A plurality of multiplexers connected to the plurality of quarter rate look ahead circuit. The plurality of multiplexers is configured to generate two speculative data streams by multiplexing respective correction coefficients of each of the plurality of latched outputs.
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公开(公告)号：US11909853B2
公开(公告)日：2024-02-20
申请号：US17696406
申请日：2022-03-16
发明人： Saikat Hazra , Avneesh Singh Verma , Raghavendra Molthati , Sunil Rajan , Tamal Das , Ankit Garg , Praveen S Bharadwaj , Sanjeeb Kumar Ghosh
CPC分类号： H04L7/0016 , G06F1/10
摘要： Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.
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4.发明授权公开(公告)号：US11906585B2
公开(公告)日：2024-02-20
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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