公开(公告)号：US11856794B2

公开(公告)日：2023-12-26

申请号：US17364378

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Sung Choi ,  Jong Uk Kim ,  Kwang Min Park ,  Zhe Wu ,  Ja Bin Lee ,  Jae Ho Jung

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10N70/841 ,  H10N70/8828

Abstract: A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

公开(公告)号：US20220059615A1

公开(公告)日：2022-02-24

申请号：US17364378

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Sung CHOI ,  Jong Uk Kim ,  Kwang Min Park ,  Zhe Wu ,  Ja Bin Lee ,  Jae Ho Jung

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.