公开(公告)号：US20240365690A1

公开(公告)日：2024-10-31

申请号：US18770547

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hsu YEN ,  Yu-Chuan HSU ,  Chen-Hui YANG

IPC分类号： H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8413 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/231 ,  H10N70/8265 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/884 ,  G11C13/0004 ,  H10B63/84 ,  H10N70/041 ,  H10N70/066 ,  H10N70/826 ,  H10N70/841 ,  H10N70/881 ,  H10N70/8833

摘要： A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

公开(公告)号：US12133476B2

公开(公告)日：2024-10-29

申请号：US18362770

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tung-Ying Lee ,  Shao-Ming Yu ,  Yu-Chao Lin

IPC分类号： H10N70/20 ,  H10N70/00

CPC分类号： H10N70/231 ,  H10N70/011 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8828

摘要： A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.

公开(公告)号：US20240357836A1

公开(公告)日：2024-10-24

申请号：US18758786

申请日：2024-06-28

申请人： SK hynix Inc.

发明人： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

IPC分类号： H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N70/24 ,  H10N70/245 ,  H10N70/253 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8828 ,  H10N70/883 ,  H10N70/8833 ,  H10N70/8836

摘要： A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

公开(公告)号：US12114580B2

公开(公告)日：2024-10-08

申请号：US18305268

申请日：2023-04-21

申请人： STMICROELECTRONICS S.r.l. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Paolo Giuseppe Cappelletti ,  Gabriele Navarro

IPC分类号： G11C11/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  H10N70/8413 ,  H10N70/8828 ,  G11C2013/008

摘要： Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.

公开(公告)号：US12089513B2

公开(公告)日：2024-09-10

申请号：US18231750

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hsu Yen ,  Yu-Chuan Hsu ,  Chen-Hui Yang

IPC分类号： H10N70/00 ,  H10B63/00 ,  H10N70/20 ,  G11C13/00

CPC分类号： H10N70/8413 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/231 ,  H10N70/8265 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/884 ,  G11C13/0004 ,  H10B63/84 ,  H10N70/041 ,  H10N70/066 ,  H10N70/826 ,  H10N70/841 ,  H10N70/881 ,  H10N70/8833

摘要： A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

公开(公告)号：US12029145B2

公开(公告)日：2024-07-02

申请号：US17201356

申请日：2021-03-15

申请人： Kioxia Corporation

发明人： Bairu Yan ,  Yoshiki Kamata ,  Kazuhiko Yamamoto

IPC分类号： H01L45/00 ,  H01L27/24 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/8828 ,  H10B63/80 ,  H10N70/043 ,  H10N70/231 ,  H10N70/826

摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.

公开(公告)号：US20240185917A1

公开(公告)日：2024-06-06

申请号：US18441881

申请日：2024-02-14

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/00 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C14/0045 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H10B12/10 ,  H10B12/20 ,  H10B63/00 ,  H10B99/00 ,  H10N70/231 ,  H10N70/883 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H10N70/8828

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US12004433B2

公开(公告)日：2024-06-04

申请号：US17810688

申请日：2022-07-05

申请人： Toshiba Global Commerce Solutions Holdings Corporation

发明人： Timothy Crockett ,  Lester Bartus, Jr.

IPC分类号： G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/826 ,  G11C13/0004 ,  G11C13/0038 ,  H10B63/20 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8828 ,  G11C2013/009

摘要： A non-volatile multi-bit storage device that includes a phase change material doped with n-type or p-type semiconductor impurities, a first set of electrodes ohmically coupled to the phase change material, a second set of electrodes configured to apply an electric field across the phase change material. To program the non-volatile multi-bit storage device, an electrical field is applied to the phase change material as crystal annealing cool down is performed. Application of the electric field during the crystal annealing cool down forms a rectified current path through the phase change material.

公开(公告)号：US11985833B2

公开(公告)日：2024-05-14

申请号：US17312702

申请日：2019-12-12

申请人： COMMISSARIAT Å L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

发明人： Khalil El Hajjam

IPC分类号： H10B63/00 ,  H10N70/00

CPC分类号： H10B63/845 ,  H10N70/066 ,  H10N70/8828 ,  H10N70/8833

摘要： A memory includes a memory cell including a planar electrode in a first plane; a floating electrode in a second plane, parallel to the first plane; a vertical electrode. The planar electrode includes a first part facing a first part of the floating electrode, the first part of the planar electrode and the first part of the second electrode being separated by a first layer of a first active material, the vertical electrode includes a part facing a second part of the floating electrode, the first part of the vertical electrode and the second part of the floating electrode being separated by a second layer of a second active material. The first active material forms a selector or a memory point and the second active material forms a memory point or a selector. The planar and floating electrodes not sharing any plane parallel to the first or second plane.

公开(公告)号：US11957067B2

公开(公告)日：2024-04-09

申请号：US17328917

申请日：2021-05-24

申请人： STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

发明人： Philippe Boivin ,  Simon Jeannot

IPC分类号： H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.