公开(公告)号：US11217327B2

公开(公告)日：2022-01-04

申请号：US17039798

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Min Kang ,  Dongku Kang ,  Kwang Won Kim ,  HyunJin Kim

IPC: G06F13/20 ,  G06F13/38 ,  G06F3/06 ,  G11C29/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C5/02 ,  G06F11/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

公开(公告)号：US11074990B2

公开(公告)日：2021-07-27

申请号：US16701205

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Min Kang ,  Dongku Kang ,  Kwang Won Kim ,  HyunJin Kim

IPC: G06F13/20 ,  G06F13/38 ,  G06F3/06 ,  G11C29/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C5/02 ,  G06F11/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.