公开(公告)号：US20200349986A1

公开(公告)日：2020-11-05

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10937471B2

公开(公告)日：2021-03-02

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06 ,  G11C16/26

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10741225B2

公开(公告)日：2020-08-11

申请号：US16802084

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.