公开(公告)号：US10937471B2

公开(公告)日：2021-03-02

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06 ,  G11C16/26

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10741225B2

公开(公告)日：2020-08-11

申请号：US16802084

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US09773566B2

公开(公告)日：2017-09-26

申请号：US15403923

申请日：2017-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Taesung Lee

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

公开(公告)号：US20200349986A1

公开(公告)日：2020-11-05

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US09576626B2

公开(公告)日：2017-02-21

申请号：US14600366

申请日：2015-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Taesung Lee

IPC: G11C7/22 ,  G11C29/02 ,  G11C29/44

CPC classification number: G11C16/32 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract translation: 非易失性存储器件包括数据通路; 以及包括连接到数据路径的多个寄存器的FIFO存储器。 多个寄存器响应于数据路径输入时钟顺序地从数据路径接收数据，并且响应于数据路径输出时钟顺序地将接收的数据输出到输入/输出焊盘。 数据路径输出时钟是通过延迟数据通道输入时钟而产生的时钟，只要延迟时间。