公开(公告)号：US10600454B2

公开(公告)日：2020-03-24

申请号：US15975266

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-su Jang ,  Man-jae Yang ,  Jeong-don Ihm ,  Go-eun Jung ,  Byung-hoon Jeong ,  Young-don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.