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    MEMORY DEVICE FOR EFFICIENTLY DETERMINING WHETHER TO PERFORM RE-TRAINING OPERATION AND MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明申请
    MEMORY DEVICE FOR EFFICIENTLY DETERMINING WHETHER TO PERFORM RE-TRAINING OPERATION AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190050159A1

    公开(公告)日：2019-02-14

    申请号：US15906266

    申请日：2018-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-joo Jung ,  Jang-woo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm

    IPC: G06F3/06

    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

    Non-volatile memory device
    6.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11114171B2

    公开(公告)日：2021-09-07

    申请号：US17010100

    申请日：2020-09-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-yeon Shin ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Jung-june Park

    IPC: G11C16/30 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  G11C7/10 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/1157

    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

    Non-volatile memory device
    7.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US10770149B2

    公开(公告)日：2020-09-08

    申请号：US16048786

    申请日：2018-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-yeon Shin ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Jung-june Park

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32

    Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

    Reference voltage generator and semiconductor device including the same
    8.
    发明授权
    Reference voltage generator and semiconductor device including the same 有权

    公开(公告)号：US10439632B2

    公开(公告)日：2019-10-08

    申请号：US16191367

    申请日：2018-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seon-kyoo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm ,  Young-don Choi

    IPC: G05F3/08 ,  H03M1/78 ,  G11C5/14

    Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

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