公开(公告)号：US20230165007A1

公开(公告)日：2023-05-25

申请号：US17951337

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Sun JANG ,  Moo Rym CHOI ,  Jung Tae SUNG

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483

Abstract: A semiconductor memory device has a peripheral logic structure including a peripheral logic substrate and a peripheral logic insulating film on the peripheral logic substrate. A cell array structure includes a cell substrate and a source structure that are sequentially stacked on the peripheral logic structure. A bypass via electrically connects the cell substrate and the peripheral logic substrate. The bypass via has a linear shape extending in at least one of first and second directions on the cell substrate. The first and second directions are parallel to an upper surface of the cell substrate.