公开(公告)号：US10013375B2

公开(公告)日：2018-07-03

申请号：US14611306

申请日：2015-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Jin Kim ,  Nak-Hee Seong ,  Hee-Seong Lee

IPC: H05K7/10 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

公开(公告)号：US09811460B2

公开(公告)日：2017-11-07

申请号：US14612516

申请日：2015-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hong Jeon ,  Hyeok-Man Kwon ,  Nak-Hee Seong

IPC: G06F12/02 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0607

Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.

公开(公告)号：US10423553B2

公开(公告)日：2019-09-24

申请号：US15996477

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Jin Kim ,  Nak-Hee Seong ,  Hee-Seong Lee

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.