Semiconductor package having mark with identification information

    公开(公告)号:US10825778B2

    公开(公告)日:2020-11-03

    申请号:US16371653

    申请日:2019-04-01

    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.

    Fan-out semiconductor package
    2.
    发明授权

    公开(公告)号:US10515916B2

    公开(公告)日:2019-12-24

    申请号:US16025267

    申请日:2018-07-02

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

    Semiconductor package
    3.
    发明授权

    公开(公告)号:US11189567B2

    公开(公告)日:2021-11-30

    申请号:US16580240

    申请日:2019-09-24

    Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

    Semiconductor package
    4.
    发明授权

    公开(公告)号:US11094660B2

    公开(公告)日:2021-08-17

    申请号:US16560311

    申请日:2019-09-04

    Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal layers connected to the first region of the redistribution layer through the plurality of first openings, respectively.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请

    公开(公告)号:US20200105679A1

    公开(公告)日:2020-04-02

    申请号:US16371653

    申请日:2019-04-01

    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.

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