公开(公告)号：US20250029935A1

公开(公告)日：2025-01-23

申请号：US18605312

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuil Hwang ,  Minkyu Kim ,  Joongsun Kim ,  Pyunghwa Han

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/18

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower redistribution substrate, an upper redistribution substrate, and a semiconductor chip between the lower redistribution substrate and the upper redistribution substrate. The lower redistribution substrate includes a lower dielectric structure, a lower redistribution pattern surrounded by the lower dielectric structure, and a lower shield structure surrounded by the lower dielectric structure and surrounding the lower redistribution pattern. The upper redistribution substrate includes an upper dielectric structure, an upper redistribution pattern surrounded by the upper dielectric structure, and an upper shield structure surrounded by the upper dielectric structure and surrounding the upper redistribution pattern.

公开(公告)号：US20250054850A1

公开(公告)日：2025-02-13

申请号：US18786824

申请日：2024-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoo Kim ,  Chobi Kim ,  Pyunghwa Han

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a first substrate, a first semiconductor device disposed on the first substrate, a dummy substrate disposed on the first substrate, spaced apart from a side surface of the first semiconductor device, and surrounding the first semiconductor device, a core module disposed in the dummy substrate, and an encapsulant surrounding the first semiconductor device and in contact with the dummy substrate, wherein the core module includes a core wiring and a module substrate, the core module is disposed on the first substrate, and a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate, and the encapsulant is disposed between the dummy substrate and the side surface of the core module.

公开(公告)号：US20250105159A1

公开(公告)日：2025-03-27

申请号：US18823171

申请日：2024-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pyunghwa Han ,  Dahee Kim ,  Bongsoo Kim ,  Chobi Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a first wiring structure, an extension structure disposed on the first wiring structure, including an extension base layer and a plurality of via structures, and having a mounting space passing through the extension base layer. The plurality of via structures include a plurality of via connection patterns, a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure, a filling insulating layer filling the mounting space, and a second wiring structure disposed on the extension structure and the filling insulating layer and electrically connected to the first wiring structure. Lowermost via connection patterns, among the plurality of via connection patterns, include a plurality of first lower connection pads, and the extension base layer includes base dams respectively passing through the plurality of first lower connection pads.