公开(公告)号：US20230081793A1

公开(公告)日：2023-03-16

申请号：US18056954

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOO BIN SONG ,  SANG WOO LEE ,  MIN HEE CHO

IPC: H01L29/08 ,  H01L29/51 ,  H01L29/417 ,  H01L29/45 ,  H01L29/24 ,  H01L29/786 ,  H01L29/267

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

公开(公告)号：US20210020628A1

公开(公告)日：2021-01-21

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHA OH ,  PIL-KYU KANG ,  KUGHWAN KIM ,  WEONHONG KIM ,  YUICHIRO SASAKI ,  SANG WOO LEE ,  SUNGKEUN LIM ,  YONGHO HA ,  SANGJIN HYUN

IPC: H01L27/06 ,  H01L27/11578 ,  H01L27/11558 ,  H01L27/24 ,  H01L23/48

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).