公开(公告)号：US20230052799A1

公开(公告)日：2023-02-16

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20210406125A1

公开(公告)日：2021-12-30

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20220012128A1

公开(公告)日：2022-01-13

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20200319962A1

公开(公告)日：2020-10-08

申请号：US16695395

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02 ,  G11C13/00

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20220027232A1

公开(公告)日：2022-01-27

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20200341843A1

公开(公告)日：2020-10-29

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.