公开(公告)号：US20230052799A1

公开(公告)日：2023-02-16

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20190004869A1

公开(公告)日：2019-01-03

申请号：US15855840

申请日：2017-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSIK KIM ,  JINWOO KIM ,  HEE HYUN NAM ,  KYUNGBO YANG ,  JI-SEUNG YOUN ,  YOUNGGEUN LEE

IPC: G06F9/50 ,  G06F3/06 ,  G06F1/30

Abstract: A storage device includes a nonvolatile memory and a controller. The controller includes a job manager circuit and a processor. The job manager circuit manages a first-type job associated with the nonvolatile memory, and the processor processes a second-type job associated with the nonvolatile memory. The job manager circuit manages the first-type job without intervention of the processor. The processor provides a management command to the job manager circuit in response to a notification received from the job manager circuit, such that the second-type job is processed.

公开(公告)号：US20210406125A1

公开(公告)日：2021-12-30

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20190004736A1

公开(公告)日：2019-01-03

申请号：US15860498

申请日：2018-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGGEUN LEE ,  JINWOO KIM ,  YOUNGSIK KIM ,  HWAN-CHUNG KIM ,  JEONGHOON CHO

IPC: G06F3/06

Abstract: A storage device includes nonvolatile memories and a controller. The controller previously manages a correspondence relationship between physical addresses indicating the memory regions and stream identifiers, before first write data is received by the controller. The controller controls the nonvolatile memories such that the first write data is stored in a first memory region of a physical address which is managed corresponding to a first stream identifier of the first write data in the correspondence relationship. The first write data is transferred to the nonvolatile memories based on the correspondence relationship, regardless of whether second write data having a second stream identifier is received by the controller.

公开(公告)号：US20170040202A1

公开(公告)日：2017-02-09

申请号：US15215578

申请日：2016-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOOJIN KIM ,  YOUNGSIK KIM ,  KUNHO SONG ,  YONGDAE HA

IPC: H01L21/683 ,  B24B37/34 ,  B24B37/30 ,  H01L21/67 ,  B24B37/10

CPC classification number: H01L21/6838 ,  B24B27/0061 ,  B24B37/10 ,  B24B37/30 ,  B24B37/345 ,  B25B11/005 ,  H01L21/68785

Abstract: A chuck table is provided and a substrate processing system including the same. The chuck table includes a base disk having a first vacuum hole, and a chuck disk disposed on the first vacuum hole. The chuck disk includes a plurality of first sectors and a first connection member connecting the first sectors to each other.

Abstract translation: 提供了一个卡盘台和一个包括该卡盘台的基板处理系统。 夹盘包括具有第一真空孔的基盘和设置在第一真空孔上的卡盘盘。 夹盘包括多个第一扇区和将第一扇区彼此连接的第一连接构件。

公开(公告)号：US20220012128A1

公开(公告)日：2022-01-13

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20200319962A1

公开(公告)日：2020-10-08

申请号：US16695395

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02 ,  G11C13/00

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20220027232A1

公开(公告)日：2022-01-27

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20200341843A1

公开(公告)日：2020-10-29

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20180294245A1

公开(公告)日：2018-10-11

申请号：US15853170

申请日：2017-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSIK KIM ,  DOOJIN KIM ,  SEOKHO LEE ,  YOUNGGON HWANG

IPC: H01L23/00 ,  B23K3/02

Abstract: A method for replacing a capillary of a wire bonding apparatus that includes a holding unit that holds a capillary includes transferring a capillary replacing unit to the wire bonding apparatus by a mobile robot in response to receiving a capillary replacement start signal from the wire bonding apparatus, separating, by the capillary replacing unit, the capillary corresponding to the replacement signal from the wire bonding apparatus, and installing, by the capillary replacing unit, a new capillary in the wire bonding apparatus.