公开(公告)号：US20220028740A1

公开(公告)日：2022-01-27

申请号：US17450726

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan KANG ,  SUN-IL SHIM ,  SEUNG HYUN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US20160247547A1

公开(公告)日：2016-08-25

申请号：US15141967

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  HAN-SOO KIM ,  WON-SEOK CHO ,  JAE-HOON JANG ,  SUN-IL SHIM ,  JAE-HUN JEONG ,  KI-HYUN KIM

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

公开(公告)号：US20200043943A1

公开(公告)日：2020-02-06

申请号：US16354448

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan KANG ,  SUN-IL SHIM ,  SEUNG HYUN

IPC: H01L27/11582 ,  H01L29/423 ,  H01L23/535 ,  H01L27/11573 ,  H01L29/45

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US20170236559A1

公开(公告)日：2017-08-17

申请号：US15586002

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  HAN-SOO KIM ,  WON-SEOK CHO ,  JAE-HOON JANG ,  SUN-IL SHIM ,  JAE-HUN JEONG ,  KI-HYUN KIM

IPC: G11C5/06 ,  H01L23/528 ,  H01L27/115

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.