公开(公告)号：US20210225871A1

公开(公告)日：2021-07-22

申请号：US17113456

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： DONG-SIK LEE ,  BYUNGJIN LEE ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

公开(公告)号：US20200212061A1

公开(公告)日：2020-07-02

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGYOON CHOI ,  DONG-SIK LEE ,  JONGWON KIM ,  GILSUNG LEE ,  EUNGSUK CHO ,  BYUNGYONG CHOI ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US20220102306A1

公开(公告)日：2022-03-31

申请号：US17240641

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HO AHN ,  JI WON KIM ,  SUNG-MIN HWANG ,  JOON-SUNG LIM ,  SUK KANG SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US20170236559A1

公开(公告)日：2017-08-17

申请号：US15586002

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  HAN-SOO KIM ,  WON-SEOK CHO ,  JAE-HOON JANG ,  SUN-IL SHIM ,  JAE-HUN JEONG ,  KI-HYUN KIM

IPC: G11C5/06 ,  H01L23/528 ,  H01L27/115

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

公开(公告)号：US20210265271A1

公开(公告)日：2021-08-26

申请号：US17027734

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISOO CHUNG ,  KANG-WON LEE ,  SUNG-MIN HWANG

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and the second block.

公开(公告)号：US20170243885A1

公开(公告)日：2017-08-24

申请号：US15591659

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang

IPC: H01L27/11582 ,  H01L21/285 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US20220223619A1

公开(公告)日：2022-07-14

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  DONG-SIK LEE ,  SUNG-MIN HWANG ,  JOON-SUNG LIM

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20190074292A1

公开(公告)日：2019-03-07

申请号：US16177566

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang

IPC: H01L27/11582 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/768 ,  H01L21/306 ,  H01L21/285 ,  H01L21/265 ,  G11C16/04

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US20190035798A1

公开(公告)日：2019-01-31

申请号：US15954151

申请日：2018-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  DONG-SIK LEE ,  JOON-SUNG LIM

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L27/11286 ,  H01L23/53295 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/0649

Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

公开(公告)号：US20160247547A1

公开(公告)日：2016-08-25

申请号：US15141967

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  HAN-SOO KIM ,  WON-SEOK CHO ,  JAE-HOON JANG ,  SUN-IL SHIM ,  JAE-HUN JEONG ,  KI-HYUN KIM

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.