公开(公告)号：US20220345137A1

公开(公告)日：2022-10-27

申请号：US17509540

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGYEOP CHOO ,  INSUNG KIM ,  WOOSEOK KIM ,  TAEIK KIM ,  SUNGHYUCK LEE ,  CHANYOUNG JEONG

IPC: H03L7/089 ,  H03L7/10

Abstract: A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.