公开(公告)号：US20200091117A1

公开(公告)日：2020-03-19

申请号：US16694316

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Eun LEE

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/528 ,  H01L23/498

Abstract: A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance.

公开(公告)号：US20180061365A1

公开(公告)日：2018-03-01

申请号：US15687177

申请日：2017-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Eun LEE ,  Hyun Ho KIM

IPC: G09G5/00 ,  H04N5/05 ,  G09G3/00 ,  G09G3/20 ,  H04N17/04

CPC classification number: G09G5/008 ,  G09G3/006 ,  G09G3/2092 ,  G09G5/006 ,  G09G2330/12 ,  G09G2350/00 ,  G09G2358/00 ,  G09G2370/04 ,  G09G2370/12 ,  G09G2370/22 ,  H04N5/05 ,  H04N17/04

Abstract: A display apparatus includes a communication interface connected with a source device, a display that displays a video signal received from the source device, and a processor that establishes connection for receiving the video signal. The processor synchronizes a clock of the display apparatus with a clock of the source device such that the connection is established and executes calibration for the video signal, when detecting an error occurring as the clock of the display apparatus fails to be synchronized.

公开(公告)号：US20150261043A1

公开(公告)日：2015-09-17

申请号：US14657668

申请日：2015-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Eun LEE ,  Dae Hee LEE ,  Young Chol LEE ,  Byoung Jin CHO

IPC: G02F1/1335 ,  G02F1/1333

CPC classification number: G02F1/133605 ,  G02F1/133308 ,  G02F1/133385

Abstract: A display apparatus is provided. The display apparatus includes a liquid crystal display panel configured to display an image; a backlight unit located at the rear of the liquid crystal display panel, and including a plurality of light sources; a bottom chassis in which the backlight unit is positioned; and a reflector located in the bottom chassis, and configured to forwardly reflect light emitted from the plurality of light sources toward the liquid crystal display panel; and a reflection angle adjuster located in each corner of the reflector, and configured to reflect light emitted from the plurality of light sources in order to cause the reflected light to be incident toward corner areas of the liquid crystal display panel.

Abstract translation: 提供一种显示装置。 显示装置包括被配置为显示图像的液晶显示面板; 位于液晶显示面板后部的背光单元，并且包括多个光源; 背光单元定位在其中的底架; 以及位于所述底盘中的反射器，其被配置为将从所述多个光源发射的光朝向所述液晶显示面板反射; 以及反射角调节器，其位于反射器的每个角部，并且被配置为反射从多个光源发射的光，以使反射光入射到液晶显示面板的拐角区域。

公开(公告)号：US20180337162A1

公开(公告)日：2018-11-22

申请号：US15798745

申请日：2017-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Eun LEE

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L23/562 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance.