公开(公告)号：US11688686B2

公开(公告)日：2023-06-27

申请号：US17163869

申请日：2021-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woonki Lee ,  Minsic Kim ,  Seunghun Oh ,  Jinhyeong Kim ,  Junyeong An ,  Jooyeon Lee ,  Sangwoo Pyo

IPC: H01L23/528 ,  H01L23/60 ,  H01L23/00 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/60 ,  H01L24/14 ,  H01L27/0296 ,  H01L2224/14135

Abstract: A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.

公开(公告)号：US11728300B2

公开(公告)日：2023-08-15

申请号：US17231111

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon-Ki Lee ,  Jae-Won Kim ,  Jongsun Jung ,  Chul-Joong Park ,  Ki-Bum Chun ,  Shivashanker Reddy Kesireddy ,  Sangwoo Pyo

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L24/06 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/06131 ,  H01L2224/06177

Abstract: A semiconductor device includes a semiconductor substrate, an integrated device ort the semiconductor substrate, a first redistribution layer on the semiconductor substrate, the first redistribution layer having first conductive patterns electrically connected to the integrated device, a second redistribution layer on the first redistribution layer, the second redistribution layer having second conductive patterns connected to the first conductive patterns, and third conductive patterns on a top surface of the second redistribution layer. The third conductive patterns include pads connected to the second conductive patterns, under-bump pads spaced apart from the pads, a grouping pattern between the pads and an outer edge of the second redistribution layer, and wiring lines that connect the under-bump pads to the pads and connect the pads to the grouping pattern.