专利检索 cpc:"H01L2224/02331" 第 1 页

1.

发明公开
EMBEDDED METAL INSULATOR METAL STRUCTURE 审中-公开

公开(公告)号：US20240363505A1

公开(公告)日：2024-10-31

申请号：US18765477

申请日：2024-07-08

申请人： Taiwan Semicondutor Manufacturing Company, Ltd.

发明人： Feng-Wei KUO , Wen-Shiang Liao

IPC分类号： H01L23/495 , H01L21/02 , H01L21/3105 , H01L21/768 , H01L23/00 , H01L23/29 , H01L23/498 , H01L23/522

CPC分类号： H01L23/49589 , H01L21/02422 , H01L21/31055 , H01L21/76832 , H01L23/29 , H01L23/49827 , H01L23/5223 , H01L24/05 , H01L24/11 , H01L28/40 , H01L28/60 , H01L2224/02331 , H01L2224/02372 , H01L2924/19041

摘要： The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

2.

发明公开
PACKAGES WITH THICK RDLS AND THIN RDLS STACKED ALTERNATINGLY 审中-公开

公开(公告)号：US20240355754A1

公开(公告)日：2024-10-24

申请号：US18758423

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Yuan Teng , Kuo Lung Pan , Yu-Chia Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chen-Hua Yu

IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L23/552

CPC分类号： H01L23/5386 , H01L21/4857 , H01L23/5381 , H01L23/5383 , H01L23/552 , H01L24/16 , H01L2224/023 , H01L2224/0233 , H01L2224/02331 , H01L2224/16227 , H01L2924/3025

摘要： A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

3.

发明授权
Semiconductor chip with redundant thru-silicon-vias 有权

公开(公告)号：US12094853B2

公开(公告)日：2024-09-17

申请号：US17963729

申请日：2022-10-11

申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC

发明人： Bryan Black , Michael Z. Su , Gamal Refai-Ahmed , Joe Siegel , Seth Prejean

IPC分类号： H01L23/48 , H01L23/00 , H01L25/065

CPC分类号： H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/03 , H01L24/11 , H01L2224/0233 , H01L2224/02331 , H01L2224/0401 , H01L2224/05022 , H01L2224/05095 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05567 , H01L2224/0557 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/17181 , H01L2225/06548 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2224/131 , H01L2924/014 , H01L2924/00014 , H01L2224/05552 , H01L2924/351 , H01L2924/00 , H01L2924/14 , H01L2924/00

摘要： A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

4.

发明公开
Die Stacking Structure and Method Forming Same 审中-公开

公开(公告)号：US20240274590A1

公开(公告)日：2024-08-15

申请号：US18648917

申请日：2024-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu , Hung-Yi Kuo , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Tsung-Yuan Yu , Ming Hung Tseng

IPC分类号： H01L25/00 , H01L21/56 , H01L21/66 , H01L21/768 , H01L23/00 , H01L25/065 , H01L25/18

CPC分类号： H01L25/50 , H01L21/561 , H01L21/563 , H01L21/76898 , H01L22/14 , H01L22/32 , H01L24/03 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/0231 , H01L2224/02331 , H01L2224/02379 , H01L2224/13024 , H01L2224/16145 , H01L2224/17181 , H01L2225/06513 , H01L2225/06541

摘要： A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

5.

发明授权
Method for forming chip structure with conductive structure 有权

公开(公告)号：US12057419B2

公开(公告)日：2024-08-06

申请号：US17874036

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Fan Huang , Mao-Nan Wang , Hui-Chi Chen , Dian-Hau Chen , Yen-Ming Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/05 , H01L24/03 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/03462 , H01L2224/0401 , H01L2224/05548 , H01L2224/13016

摘要： A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.

6.

发明授权
Redistribution layer metallic structure and method 有权

公开(公告)号：US12040293B2

公开(公告)日：2024-07-16

申请号：US18055241

申请日：2022-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih Wei Bih , Sheng-Wei Yeh , Yen-Yu Chen , Wen-Hao Cheng , Chih-Wei Lin , Chun-Chih Lin

IPC分类号： H01L23/532 , H01L21/02 , H01L23/00 , H01L23/525

CPC分类号： H01L24/05 , H01L21/02068 , H01L24/03 , H01L2224/02321 , H01L2224/02331 , H01L2224/02372 , H01L2224/02377 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/035 , H01L2224/0391 , H01L2224/05008 , H01L2224/05083 , H01L2224/05181 , H01L2224/05187 , H01L2224/05188 , H01L2224/05624 , H01L2224/05647 , H01L2924/04953 , H01L2924/0535 , H01L2924/05994

摘要： The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

7.

发明授权
Display device with alternating fan-out lines 有权

公开(公告)号：US12022699B2

公开(公告)日：2024-06-25

申请号：US17189561

申请日：2021-03-02

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Tae Jong Eom , Chun Gi You

IPC分类号： H10K59/131 , H01L23/00 , H10K59/121

CPC分类号： H10K59/131 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/02331 , H01L2224/02373 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/05569 , H01L2224/16145 , H01L2224/32148 , H01L2224/73203 , H01L2924/01022 , H01L2924/01042 , H10K59/1213

摘要： A display device includes: a substrate; sub-pixels on the substrate; data lines connected to the sub-pixels; a display driving circuit supplying data voltages to the data lines; and fan-out lines on the substrate and connecting the data lines and the display driving circuit. Each of the sub-pixels includes a first transistor including a first active layer on the substrate and including a silicon semiconductor and a first gate electrode on the first active layer, and a second transistor including a second active layer on the substrate and including an oxide semiconductor and a second gate electrode on the second active layer. The fan-out lines include first fan-out lines and second fan-out lines alternately arranged each other in one direction. The first fan-out lines are arranged on the same layer as the first gate electrode, and the second fan-out lines are arranged on the same layer as the second gate electrode.

8.

发明授权
Package structure with through-via in molding compound and dielectric layer 有权

公开(公告)号：US12009322B2

公开(公告)日：2024-06-11

申请号：US17670481

申请日：2022-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Hsuan Tai , Ting-Ting Kuo , Yu-Chih Huang , Chih-Wei Lin , Hsiu-Jen Lin , Chih-Hua Chen , Ming-Da Cheng , Ching-Hua Hsieh , Hao-Yi Tsai , Chung-Shi Liu

IPC分类号： H01L21/683 , H01L23/00 , H01L23/31

CPC分类号： H01L24/02 , H01L21/6835 , H01L21/6836 , H01L23/3114 , H01L23/3135 , H01L24/19 , H01L24/96 , H01L24/97 , H01L23/3128 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68372 , H01L2224/02311 , H01L2224/02319 , H01L2224/02331 , H01L2224/02371 , H01L2224/02379 , H01L2224/02381 , H01L2224/12105

摘要： A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

9.

发明授权
Redistribution lines with protection layers and method forming same 有权

公开(公告)号：US12009256B2

公开(公告)日：2024-06-11

申请号：US18338095

申请日：2023-06-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Da Cheng , Wen-Hsiung Lu , Chin Wei Kang , Yung-Han Chuang , Lung-Kai Mao , Yung-Sheng Lin

IPC分类号： H01L21/768 , H01L23/00

CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76852 , H01L21/76871 , H01L24/05 , H01L24/13 , H01L24/32 , H01L2224/0231 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022

摘要： A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.