公开(公告)号：US20200379541A1

公开(公告)日：2020-12-03

申请号：US16994894

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOK-JU YOON ,  Nak-Woo Sung ,  Seung-Chull Suh ,  Taek-ki Kim ,  Jae-Joon Yoo ,  Eun-Ok Jo

IPC: G06F1/329 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/324

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

公开(公告)号：US11656675B2

公开(公告)日：2023-05-23

申请号：US17739732

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Ju Yoon ,  Nak-Woo Sung ,  Seung-Chull Suh ,  Taek-Ki Kim ,  Jae-Joon Yoo ,  Eun-Ok Jo

IPC: G06F1/329 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F15/167 ,  G06F9/50

CPC classification number: G06F1/329 ,  G06F1/324 ,  G06F1/3228 ,  G06F1/3296

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

公开(公告)号：US11271897B2

公开(公告)日：2022-03-08

申请号：US16504757

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soungkwan Kimn ,  Taejin Kim ,  Seung-Chull Suh

IPC: H04L29/12 ,  H04L61/2503

Abstract: An electronic apparatus includes a first translation table that stores information of a first address and a second address; a second translation table that, in response to a condition being satisfied, stores the information of the first address and the second address based on the first translation table; at least one processor configured to translate the first address of a first packet to the second address based on the first translation table; and a forwarding manager that, in response to a second packet including the first address being received and the information of the first address and the second address being stored in the second translation table, translates the first address of the second packet to the second address based on the second translation table, prior to allocating the second packet to the at least one processor.

公开(公告)号：US11327555B2

公开(公告)日：2022-05-10

申请号：US16994894

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Ju Yoon ,  Nak-Woo Sung ,  Seung-Chull Suh ,  Taek-Ki Kim ,  Jae-Joon Yoo ,  Eun-Ok Jo

IPC: G06F1/329 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F15/167 ,  G06F9/50

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

公开(公告)号：US10747297B2

公开(公告)日：2020-08-18

申请号：US15797383

申请日：2017-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Ju Yoon ,  Nak-Woo Sung ,  Seung-Chull Suh ,  Taek-Ki Kim ,  Jae-Joon Yoo ,  Eun-Ok Jo

IPC: G06F1/329 ,  G06F1/324 ,  G06F1/3228 ,  G06F15/167 ,  G06F1/3296

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.