公开(公告)号：US09336877B2

公开(公告)日：2016-05-10

申请号：US14504914

申请日：2014-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yun Lee ,  Sun Woo-Jung ,  Kwang-Jin Lee ,  Dong-Hoon Jeong ,  Beak-Hyung Cho

IPC: G11C8/08 ,  G11C13/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C13/0026 ,  G11C13/004 ,  G11C2211/5623 ,  G11C2213/71

Abstract: A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.

Abstract translation: 非易失性存储器件利用可变电阻元件。 非易失性存储器件包括多个存储体，并且布置成跨越多个存储体的第一至第三写入全局位线。 多个存储体中的每一个包括使用电阻材料的多个非易失性存储单元。 第一，第二和第三写全局位线按顺序彼此直接相邻布置。 当在写入周期期间向第一写入全局位线提供写入电流时，固定的电压被施加到第二写入全局位线，而第三个全局位线被浮置。