公开(公告)号：US09519487B2

公开(公告)日：2016-12-13

申请号：US14161838

申请日：2014-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Han Lee ,  Sung-Chul Yoon ,  Sung-Hoo Choi ,  Jae-Sop Kong ,  Kee-Moon Chun

IPC: G06F9/38 ,  G06F15/78 ,  G06F9/30

CPC classification number: G06F9/3877 ,  G06F15/7807

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

Abstract translation: 片上系统（SoC）包括从属知识产权（IP）块，主IP块和更新控制单元。 从属IP块被配置为基于存储在第一存储单元中的第一控制信息对第一数据执行第一处理。 主IP块被配置为响应于接收到通过对第一数据执行第一处理获得的第一处理结果而对第二数据执行第二处理。 执行第二处理是基于存储在第二存储单元中的第二控制信息。 更新控制单元被配置为响应于执行第一处理而确定第一控制信息的更新时间或第二控制信息的更新时间，并执行第二处理。

公开(公告)号：US09754352B2

公开(公告)日：2017-09-05

申请号：US14644383

申请日：2015-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Chul Yoon ,  Min-soo Kim ,  Jae-Sop Kong

IPC: G06T3/40 ,  H04N5/262

CPC classification number: G06T3/4092 ,  G06T3/4007 ,  G06T2200/16 ,  G06T2200/28 ,  G06T2210/36 ,  H04N5/2628

Abstract: A reconfigurable image scaling circuit includes a horizontal scalar, a bufferer, and a vertical scalar. The horizontal scalar is configured to generate a horizontally scaled image data by scaling an input image data horizontally. The bufferer includes a mapper and a plurality of buffers. The plurality of the buffers are configured to store the horizontally scaled image data. The vertical scalar is configured to generate an output image data by scaling the horizontally scaled image vertically using a vertical scaling method.

公开(公告)号：US10600145B2

公开(公告)日：2020-03-24

申请号：US14488621

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Chul Yoon ,  Min-Soo Kim ,  Jae-Sop Kong

IPC: G09G5/00 ,  G06T3/40 ,  G06T3/60 ,  G06T3/00 ,  G06T1/60 ,  G06T1/20 ,  H04N5/262

Abstract: An image processor comprises first scaling logic that receives image data comprising a first number of lines and generates first scaled image data by scaling down the image data in a first direction, a rotation buffer that has storage capacity for storing a second number of lines less than the first number of lines and stores the first scaled image data in a rotated state, and second scaling logic that generates second scaled image data by scaling down the first scaled image data in a second direction different from the first direction.

公开(公告)号：US10079004B2

公开(公告)日：2018-09-18

申请号：US14547668

申请日：2014-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Chul Yoon ,  Jong-Ho Roh ,  Jae-Sop Kong

IPC: G09G5/391 ,  G09G5/00

CPC classification number: G09G5/391 ,  G09G5/005 ,  G09G5/006 ,  G09G2340/0407 ,  G09G2350/00 ,  G09G2370/04

Abstract: A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.