公开(公告)号：US20220208965A1

公开(公告)日：2022-06-30

申请号：US17379051

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki MIN ,  Donghyun ROH ,  Chaeho NA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US20240290790A1

公开(公告)日：2024-08-29

申请号：US18509736

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki MIN

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: A semiconductor device may include a substrate including a first dummy region and a second dummy region spaced apart from each other and a trench between the first dummy region and the second region, a device isolation layer filling the trench between the first dummy region and the second dummy region, a dielectric structure on the device isolation layer; an interlayer dielectric layer on the dielectric structure, a power line on the interlayer dielectric layer, a power delivery network layer on a bottom surface of the substrate, and a through via extending from the power delivery network layer through the dielectric structure to the power line. An upper portion of the device isolation layer may include a protrusion and a trough, and the dielectric structure may cover the protrusion and the trough.

公开(公告)号：US20220122894A1

公开(公告)日：2022-04-21

申请号：US17567403

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunki MIN ,  Donghyun ROH

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/764

Abstract: A method for manufacturing a semiconductor device includes forming a first active fin and a second active fin on a first active region and a second active region of a substrate, respectively, forming a device isolation layer to cover sidewalls of lower portions of the first active fin and the second active fin, forming a first liner layer and a second liner layer to cover upper portions of the first active fin and the second active fin, respectively, forming a first gate electrode and a second gate electrode on the first active fin and the second active fin, respectively, and forming a first source/drain region and a second source/drain region on the first active fin and the second active fin, respectively. The first liner layer includes a different material from a material of the second liner layer.

公开(公告)号：US20180204762A1

公开(公告)日：2018-07-19

申请号：US15828728

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunki MIN ,  Songe KIM ,  Koungmin RYU ,  Je-Min YOO

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/76229 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having a first active pattern and a second active pattern, the first active pattern including a first recess region dividing an upper portion thereof into a first portion and a second portion, the second active pattern including a second recess region dividing an upper portion thereof into a first portion and a second portion, a first insulating pattern covering an inner sidewall of the first recess region, and a second insulating pattern covering an inner sidewall of the second recess region. The first insulating pattern and the second insulating pattern include the same insulating material, and a volume fraction of the first insulating pattern with respect to a volume of the first recess region is smaller than a volume fraction of the second insulating pattern with respect to a volume of the second recess region.