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公开(公告)号:US20230282538A1
公开(公告)日:2023-09-07
申请号:US18137803
申请日:2023-04-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ae-Nee JANG , Seung-Duk BAEK , Tae-Heon KIM
IPC: H01L23/367 , H01L23/31 , H01L23/48 , H01L23/373 , H01L23/498 , H01L23/538
CPC classification number: H01L23/367 , H01L23/3157 , H01L23/481 , H01L23/3738 , H01L23/49827 , H01L23/5384 , H01L23/49816
Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.
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公开(公告)号:US20210296200A1
公开(公告)日:2021-09-23
申请号:US17340197
申请日:2021-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ae-Nee JANG , Seung-Duk BAEK , Tae-Heon KIM
IPC: H01L23/367 , H01L23/31 , H01L23/48 , H01L23/373 , H01L23/498 , H01L23/538
Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.
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