公开(公告)号：US20230147016A1

公开(公告)日：2023-05-11

申请号：US17959663

申请日：2022-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegook KIM ,  Woojin NA ,  Taegeun YOO ,  Hyeseung YU ,  Jaejun LEE

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C7/1072

Abstract: Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.