公开(公告)号：US20210066148A1

公开(公告)日：2021-03-04

申请号：US16814455

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Taewon YOO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20250105100A1

公开(公告)日：2025-03-27

申请号：US18977556

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Minjung KIM ,  Dongkyu KIM ,  Taewon YOO

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US20210202423A1

公开(公告)日：2021-07-01

申请号：US17018259

申请日：2020-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  Taewon YOO ,  Myungkee CHUNG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.

公开(公告)号：US20230033087A1

公开(公告)日：2023-02-02

申请号：US17682465

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim SUK ,  Taewon YOO ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate including a first, second and third under-bump patterns; a semiconductor chip provided on the first substrate; conductive structures provided on the first substrate; and a second substrate provided on the semiconductor chip and the conductive structures. The third under-bump pattern is electrically isolated from the first and second under-bump patterns. The conductive structures include: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and provided adjacent to the first and second conductive structures. The third conductive structure is provided between the first conductive structure and the second conductive structure, the first under-bump pattern is wider than the third under-bump pattern, and the second under-bump pattern is wider than the third under-bump pattern.

公开(公告)号：US20220020653A1

公开(公告)日：2022-01-20

申请号：US17488662

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Taewon YOO

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20210257325A1

公开(公告)日：2021-08-19

申请号：US16923428

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Taewon YOO ,  Myungkee CHUNG

IPC: H01L23/00

Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

公开(公告)号：US20200373216A1

公开(公告)日：2020-11-26

申请号：US16710841

申请日：2019-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon YOO ,  Hyunsoo CHUNG ,  Myungkee CHUNG

IPC: H01L23/36 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package is provided including a first semiconductor package including a first semiconductor chip. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor package is disposed on the first semiconductor package. The second semiconductor package includes a second redistribution layer including a redistribution line. A second semiconductor chip is disposed on the second redistribution layer. A thermal pillar is disposed on the second redistribution layer. A heat radiator is disposed on the second semiconductor package and connected to the thermal pillar. The redistribution line is connected to the first semiconductor chip.