公开(公告)号：US20250105100A1

公开(公告)日：2025-03-27

申请号：US18977556

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Minjung KIM ,  Dongkyu KIM ,  Taewon YOO

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US20230351719A1

公开(公告)日：2023-11-02

申请号：US18315072

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eega Revanth RAJ ,  Sai Karthikey PENTAPATI ,  Raj Narayana GADDE ,  Anushka GUPTA ,  Dongkyu KIM ,  Kwangpyo CHOI

IPC: G06V10/42 ,  G06V10/44 ,  G06V10/94

CPC classification number: G06V10/42 ,  G06V10/44 ,  G06V10/94

Abstract: An electronic device for determining global attention in a deep learning model is provided. The electronic device includes a hardware accelerator, a low-complex global attention generator, a parallel switch, and a series switch. The hardware accelerator is configured to process each tile of a full-frame image and the low complex global attention generator is configured to generate a channel attention map of the full-frame image. The parallel switch is configured to bypass a connection of the channel attention map with the hardware accelerator and a series switch, configured to gate the connection of the channel attention map with the hardware accelerator.

公开(公告)号：US20210020600A1

公开(公告)日：2021-01-21

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho JANG ,  Gwangjae JEON ,  Dongkyu KIM ,  Jungho PARK ,  Seokhyun LEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

公开(公告)号：US20240145375A1

公开(公告)日：2024-05-02

申请号：US18311405

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Dongkyu KIM ,  Inhyung SONG

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/02164 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2225/1041 ,  H01L2924/182

Abstract: A semiconductor package includes an interposer including a first redistribution layer and a second redistribution layer that is on the first redistribution layer and is electrically coupled to the first redistribution layer; and a semiconductor chip on the interposer. The first redistribution layer includes a first organic insulating layer and a plurality of first conductors in the first organic insulating layer. The second redistribution layer includes a second organic insulating layer, a first silicon insulating layer on the second organic insulating layer, and a plurality of second conductors penetrating through both the second organic insulating layer and the first silicon insulating layer. The semiconductor chip includes a second silicon insulating layer and a plurality of third conductors in the second silicon insulating layer. The second conductors are directly bonded to separate, respective third conductors and the first silicon insulating layer is directly bonded to the second silicon insulating layer.

公开(公告)号：US20240065003A1

公开(公告)日：2024-02-22

申请号：US18295324

申请日：2023-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu KIM ,  Kyounglim SUK ,  Hyeonseok LEE ,  Hyeonjeong HWANG

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31

CPC classification number: H10B80/00 ,  H01L23/5226 ,  H01L24/16 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/16145 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13155 ,  H01L2224/1318 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13171 ,  H01L2224/13111 ,  H01L2224/13166 ,  H01L2224/1146

Abstract: A semiconductor package includes a memory chip having chip pads on a first surface thereof. A redistribution layer is formed on the first surface of the memory chip. The redistribution layer is electrically connected to the chip pads. The redistribution layer has first redistribution pads on a first surface of the redistribution layer in a first region and a plurality of second redistribution pads on the first surface of the redistribution layer in a second region thereof. A processor chip is disposed on the first region of the redistribution layer and is electrically connected to the first redistribution pads. A sealing member is disposed on the first surface of the redistribution layer and covers the processor chip. Conductive structures are on the second region and penetrate through the sealing member and extend upwardly in a vertical direction away from the second redistribution pads.

公开(公告)号：US20230031143A1

公开(公告)日：2023-02-02

申请号：US17723055

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook BAEK ,  Sangwon LEE ,  Taekeun KANG ,  Dongkyu KIM ,  Gihyeon BAE ,  Jungmin LEE ,  Youngo PARK ,  Kwangpyo CHOI

IPC: G06T3/40 ,  G06T7/00

Abstract: An image processing apparatus for performing image quality processing on an image includes: a memory configured to store one or more instructions; and a processor configured to execute the one or more instructions stored in the memory to: obtain a first image by downscaling an input image by using a downscale network; extract first feature information corresponding to the first image by using a feature extraction network; obtain a second image by performing image quality processing on the first image based on the first feature information, by using an image quality processing network; and obtain an output image by upscaling the second image, extracting second feature information corresponding to the input image, and performing image quality processing on the upscaled second image based on the second feature information, by using an upscale network.

公开(公告)号：US20220367403A1

公开(公告)日：2022-11-17

申请号：US17711359

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Dongkyu KIM ,  Kyounglim SUK ,  Hyeonjeong HWANG

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

公开(公告)号：US20160291928A1

公开(公告)日：2016-10-06

申请号：US15088595

申请日：2016-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyun LEE ,  Younghoon KWAK ,  Dongkyu KIM ,  Yu-Jeong JEON

IPC: G06F3/16 ,  H04M1/725 ,  G06F3/0484 ,  G06F3/0488 ,  G06F3/041

CPC classification number: H04M1/72519 ,  G06F3/0488 ,  G06F2203/04104 ,  G06F2203/04803 ,  H04M2250/22

Abstract: An electronic device and a method are provided for controlling volume. The electronic device includes a touch screen including a main area on a front surface of the electronic device and an auxiliary area formed on a side of the main area; and a controller configured to detect a touch area contacted on the auxiliary area in a call mode, to determine the auxiliary area as a volume control area based on the touch area, and to control volume according to a touch event input in the volume control area.

Abstract translation: 提供了用于控制音量的电子设备和方法。 电子设备包括触摸屏，其包括在电子设备的前表面上的主区域和形成在主区域一侧的辅助区域; 以及控制器，被配置为在呼叫模式中检测与所述辅助区域接触的触摸区域，以基于所述触摸区域将所述辅助区域确定为音量控制区域，以及根据在所述音量控制区域中输入的触摸事件来控制音量 。

公开(公告)号：US20160240149A1

公开(公告)日：2016-08-18

申请号：US15045690

申请日：2016-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunseok KIM ,  Younghoon KWAK ,  Dongkyu KIM ,  Sang-Hyen PARK ,  Seungyun LEE

IPC: G09G3/34 ,  G04G21/08 ,  G04G9/00 ,  G09G3/36 ,  G06F1/32

CPC classification number: G04G21/08 ,  G04C17/0091 ,  G04G9/0023 ,  G04G11/00 ,  G04G21/02 ,  G04G21/04 ,  G04R20/26 ,  G06F1/163 ,  G06F1/3218 ,  G06F1/3265 ,  G09G3/3648 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2354/00

Abstract: An apparatus and a method for displaying information are provided. The method includes, in a standby mode, maintaining a display in a transparent state, the display covering a clock module including hands of a clock, in response to a display event, adjusting transparency of a display area on the display, and displaying information corresponding to the display event on the display area.

Abstract translation: 提供了一种用于显示信息的装置和方法。 该方法包括在备用模式下，将显示器保持在透明状态，覆盖包括时钟指针的时钟模块的显示器响应于显示事件，调整显示器上的显示区域的透明度，并且显示对应的信息 到显示区域上的显示事件。

公开(公告)号：US20230026972A1

公开(公告)日：2023-01-26

申请号：US17700818

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Dongkyu KIM ,  Shang-Hoon SEO ,  Jaegwon JANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.