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    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210202423A1

    公开(公告)日：2021-07-01

    申请号：US17018259

    申请日：2020-09-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo CHUNG ,  Taewon YOO ,  Myungkee CHUNG

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532

    Abstract: A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250022787A1

    公开(公告)日：2025-01-16

    申请号：US18440215

    申请日：2024-02-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo CHUNG ,  Kwang-Soo Kim ,  Jaesic Lee

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

    Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip, and a connection die. A hybrid bonding may be established between the connection die and the first semiconductor chip and between the connection die and the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having first and second surfaces. The first surface is closer than the second surface to the connection die. The second semiconductor chip includes a second semiconductor substrate having third and fourth surfaces. The third surface is closer than the fourth surface to the connection die. The first and second semiconductor chips further include a power distribution wiring layer on the second surface of the first semiconductor chip and the fourth surface of the second semiconductor substrate.

    STACK SEMICONDUCTOR PACKAGE
    9.
    发明公开
    STACK SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240063155A1

    公开(公告)日：2024-02-22

    申请号：US18296500

    申请日：2023-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo CHUNG ,  Joonghyun Baek ,  Hyungu Kang ,  Taeyoung Kim ,  Jaekyu Sung ,  Cheolwoo Lee

    IPC: H01L23/00 ,  H10B80/00

    CPC classification number: H01L24/06 ,  H10B80/00 ,  H01L2224/0401 ,  H01L2224/06519 ,  H01L2924/1431 ,  H01L2924/1434

    Abstract: A stack semiconductor package including a base chip, at least two semiconductor chips stacked on the base chip, and a sealing material sealing the at least two semiconductor chips on the base chip may be provided. The at least two semiconductor chips may include an uppermost semiconductor chip and at least one under the uppermost semiconductor chip, the first semiconductor chip includes through electrodes at a central portion thereof along a first direction, the through electrodes arranged along a second direction perpendicular to the first direction, upper dummy pads on outer portions of a back side of the first semiconductor chip, the outer portions being a non-active surface of the first semiconductor chip and being at both sides of the central portion in the first direction, and a dummy pattern connecting the upper dummy pads with each other on the back side.

    SEMICONDUCTOR PACKAGE
    10.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230069511A1

    公开(公告)日：2023-03-02

    申请号：US17834066

    申请日：2022-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

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