公开(公告)号：US20180292989A1

公开(公告)日：2018-10-11

申请号：US15869769

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HOON LEE ,  EUN-SUK CHO ,  WOO-PYO JEONG ,  SANG-WAN NAM ,  JUNG-HO SONG ,  YUN-HO HONG ,  JAE-HOON LEE

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/265 ,  H01L27/02

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  H01L21/265 ,  H01L27/0207 ,  H01L27/11573 ,  H01L27/11582

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.