公开(公告)号：US20220352309A1

公开(公告)日：2022-11-03

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  DAHYE KIM ,  DONGMYOUNG KIM ,  DONGWOO KIM ,  YONGJUN NAM ,  SANGMOON LEE ,  INGYU JANG ,  SUJIN JUNG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

公开(公告)号：US20220416086A1

公开(公告)日：2022-12-29

申请号：US17711914

申请日：2022-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJIN KIM ,  SANGMOON LEE ,  JINBUM KIM ,  YONGJUN NAM

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.