公开(公告)号：US10102125B2

公开(公告)日：2018-10-16

申请号：US14864461

申请日：2015-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Seok Cha ,  Ki Jo Jung ,  Ki Chul Noh ,  Yeong Kyun Lee ,  Yong Tae Jeon ,  Han Chan Jo

IPC: G06F13/12 ,  G06F12/0811 ,  G06F13/42 ,  G06F13/40 ,  G06F12/1009

Abstract: A peripheral component interconnect (PCI) device includes a first memory which includes a plurality of page buffers, a base address register which includes a plurality of base addresses, and a first address translation unit which translates each of the plurality of base addresses to a corresponding one of a plurality of virtual addresses. A map table includes a plurality of map table entries each accessed in correspondence to each of the plurality of virtual addresses, and maps each of the plurality of virtual addresses onto a physical address of physical addresses of the plurality of page buffers. The first address translation unit translates each of the plurality of virtual addresses to a corresponding one of the physical addresses using the map table.

公开(公告)号：US10002085B2

公开(公告)日：2018-06-19

申请号：US14938994

申请日：2015-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Seok Cha ,  Yong Tae Jeon ,  Ki Chul Noh ,  Ki Jo Jung ,  Chandrashekar Tandavapura Jagadish ,  Vamshi Krishna Komuravelli

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/16 ,  G06F13/4068 ,  G06F13/4282

Abstract: A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.