公开(公告)号：US20240283261A1

公开(公告)日：2024-08-22

申请号：US18459957

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo CHUNG ,  Daeyong HAN

IPC: H02J7/00 ,  G01R31/52

CPC classification number: H02J7/0029 ,  G01R31/52 ,  H02J7/0047 ,  H02J7/00712

Abstract: A charger integrated circuit includes a plurality of power transistors configured to transmit one of a battery voltage, a charging voltage, and a load voltage as an internal power supply voltage based on a voltage selection control signal, a voltage selector configured to, determine a highest voltage among a battery voltage, a charging voltage, and a load voltage, and transmit the voltage selection control signal to the plurality of power transistors based on results of the determination, a short current limiter configured to, output the internal power supply voltage as a chip voltage, and limit a level of a short circuit current corresponding to the chip voltage in response to a current control signal, and a power drop sensor configured to generate the current control signal in response to a voltage level of the chip voltage being lower than a voltage level of a reference voltage.

公开(公告)号：US20220415954A1

公开(公告)日：2022-12-29

申请号：US17836108

申请日：2022-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinju JEON ,  Youngwoo CHUNG ,  Hanseok KIM ,  Heegeun JEONG

IPC: H01L27/146

Abstract: An image sensor includes: a first semiconductor chip having a pixel region, a peripheral region, and a first wiring layer; and a second semiconductor chip combined with the first semiconductor chip, and including a second wiring layer, wherein the pixel region includes an active pixel region and a dummy pixel region, wherein the pixels are separated from one another by deep trench isolations (DTI) passing through a silicon layer, wherein a backside contact applying a negative (−) voltage to a conductive layer of each of the DTIs is arranged in the dummy pixel region and passes through the silicon layer, wherein the backside contact contacts the conductive layer of each of the DTIs, and wherein a through via is formed in the peripheral region, and wiring lines of the first wiring layer are connected to wiring lines of a second wiring layer through the through via.