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公开(公告)号：US11513548B2
公开(公告)日：2022-11-29
申请号：US17200017
申请日：2021-03-12
发明人： Chisung Bae , Hyungmin Gi , Yeohoon Yoon , Yoonmyung Lee
摘要： An apparatus and method for tracking maximum power are disclosed. The apparatus is configured to track a maximum power at a certain node of an electronic circuit, adjust an impedance of the electronic circuit such that power at the node is maximal, and adjust an impedance of the electronic circuit by comparing power at two points in time to increase power. The apparatus for tracking a maximum power, includes a charge sharing capacitor connected to an initial capacitor in parallel, a first switch disposed between the initial capacitor and an energy harvesting power supply, a second switch disposed between the initial capacitor and the charge sharing capacitor, a third switch disposed between the energy harvesting power supply and a comparator, and a switched-capacitor power converting circuit configured to control the initial capacitor.
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公开(公告)号：US11557560B2
公开(公告)日：2023-01-17
申请号：US17223601
申请日：2021-04-06
发明人： Yeohoon Yoon , Hyungsun Jang
IPC分类号： H01L23/00 , H01L23/498
摘要： A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.
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公开(公告)号：US20220059492A1
公开(公告)日：2022-02-24
申请号：US17223601
申请日：2021-04-06
发明人： Yeohoon Yoon , Hyungsun Jang
IPC分类号： H01L23/00 , H01L23/498
摘要： A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.
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