公开(公告)号：US11989422B2

公开(公告)日：2024-05-21

申请号：US17733559

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changjun Lee ,  Youngmin Lee ,  Eunkak Kim ,  Jeongmin Seo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device, an electronic device, and a method of operating the memory device are provided. The memory device includes: a volatile memory including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and configured to provide output data stored in target memory cells, among the plurality of memory cells, based on a first read command and an address received from a host; a recovery logic circuit configured to provide hint data indicating first bit lines to which defective cells are connected, and second bit lines to which normal cells are connected, among the plurality of bit lines; and an Error Correction Circuit (ECC) configured to generate corrected data by correcting an error in the output data based on the output data and the hint data, and to provide the corrected data to the host.

公开(公告)号：US20230126954A1

公开(公告)日：2023-04-27

申请号：US17733559

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Changjun Lee ,  Youngmin Lee ,  Eunkak Kim ,  Jeongmin Seo

IPC: G06F3/06

Abstract: A memory device, an electronic device, and a method of operating the memory device are provided. The memory device includes: a volatile memory including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and configured to provide output data stored in target memory cells, among the plurality of memory cells, based on a first read command and an address received from a host; a recovery logic circuit configured to provide hint data indicating first bit lines to which defective cells are connected, and second bit lines to which normal cells are connected, among the plurality of bit lines; and an Error Correction Circuit (ECC) configured to generate corrected data by correcting an error in the output data based on the output data and the hint data, and to provide the corrected data to the host.

公开(公告)号：US20240069790A1

公开(公告)日：2024-02-29

申请号：US18137036

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin AHN ,  Seoyeong Lee ,  Dongwoo Shin ,  Changjun Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: An operating method of a storage device including a memory controller and a non-volatile memory, the method including: performing a first read in response to a read request by reading data from the non-volatile memory using a default read voltage set; and performing a second read when the first read fails, by calculating a degradation compensation level, using a weight table, offset table, and displacement level, calculating a history read voltage set by performing an operation on the default read voltage set and degradation compensation level, and reading the data using the history read voltage set, wherein the weight table includes weights preset according to word line groups and state read voltages, the offset table includes offset levels preset according to the word line groups and the state read voltages, and the displacement level corresponds to a difference between a default read voltage level and an optimal read voltage level.

公开(公告)号：US20220197510A1

公开(公告)日：2022-06-23

申请号：US17395582

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Lee ,  Changjun Lee ,  Jinmyung Yoon ,  Gyuseok Choe ,  Seongwan Hong

IPC: G06F3/06

Abstract: An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.

公开(公告)号：US12135897B2

公开(公告)日：2024-11-05

申请号：US18137036

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Ahn ,  Seoyeong Lee ,  Dongwoo Shin ,  Changjun Lee

IPC: G06F3/06

Abstract: An operating method of a storage device including a memory controller and a non-volatile memory, the method including: performing a first read in response to a read request by reading data from the non-volatile memory using a default read voltage set; and performing a second read when the first read fails, by calculating a degradation compensation level, using a weight table, offset table, and displacement level, calculating a history read voltage set by performing an operation on the default read voltage set and degradation compensation level, and reading the data using the history read voltage set, wherein the weight table includes weights preset according to word line groups and state read voltages, the offset table includes offset levels preset according to the word line groups and the state read voltages, and the displacement level corresponds to a difference between a default read voltage level and an optimal read voltage level.