公开(公告)号：US20020168935A1

公开(公告)日：2002-11-14

申请号：US10061091

申请日：2002-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Chul Han

IPC: H04B001/60

CPC classification number: H04B1/7115 ,  H04B1/712 ,  H04B2201/70707

Abstract: A symbol combining device for multi-path diversity includes a plurality of demodulation circuits for demodulating received signals, a common memory for storing outputs of the demodulation circuits, a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs, and a memory controller for controlling the common memory to timely separate the write and read operations. To timely separate the write and read operations, the memory controller controls the common memory in order that the demodulation circuits sequentially access the common memory and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially. Because the deskewer of the symbol combining device is constructed of a single memory, not FIFO by channels, the required number of gates is about 40% of the FIFO by channels, and the size of the symbol combining device is reduced to 40%. Further, the symbol combining device can be easily adaptable to change of the number of channels for various services.

Abstract translation: 用于多径分集的符号组合装置包括用于解调接收信号的多个解调电路，用于存储解调电路的输出的公共存储器，用于接收对应于解调电路的公共存储器的输出并用于组合的符号组合器 输出端以及用于控制公共存储器以及时分离写入和读取操作的存储器控​​制器。 为了及时分离写入和读取操作，存储器控制器控制公共存储器，以便解调电路顺序地访问公用存储器，并将解调电路的合成输出写入公共存储器中，并且符号组合器读取 顺序地在公共存储器中写入解调电路。 由于符号组合设备的电路板由单个存储器构成，而不是通过信道FIFO，因此所需数量的栅极大约为FIFO的40％，符号组合器件的大小减少到40％。 此外，符号组合装置可以容易地适应于各种服务的频道数量的改变。

公开(公告)号：US20030103556A1

公开(公告)日：2003-06-05

申请号：US09991514

申请日：2001-11-16

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Sung-Chul Han

IPC: H04K001/00

CPC classification number: H04B1/7115 ,  H04B1/7117 ,  H04B2201/7071

Abstract: A rake receiver for high data rate communications systems is provided that is able to share resources between demodulating branches without using independent hardware resources for each finger. The rake receiver of the present invention uses less circuitry while keeping functional equivalence, and it requires relatively smaller additional area when increasing the number of demodulating branches, thereby having a significantly smaller size, being able to track more demodulating paths for increasing performance, and being less complex as compared to conventional rake receivers for high data rate communications systems.

Abstract translation: 提供了一种用于高数据速率通信系统的耙式接收机，其能够在解调分支之间共享资源，而不需要为每个手指使用独立的硬件资源。 本发明的耙式接收机在保持功能等同性的同时使用更少的电路，并且当增加解调分支的数量时需要相对较小的附加面积，从而具有明显更小的尺寸，能够跟踪更多的解调路径以提高性能，并且 与用于高数据速率通信系统的常规耙式接收机相比，复杂度较低。

公开(公告)号：US20040047333A1

公开(公告)日：2004-03-11

申请号：US10426016

申请日：2003-04-30

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Sung-Chul Han ,  Joo-Kwang Kim ,  Chae-Man Lim

IPC: H04J003/06 ,  H04B007/216

CPC classification number: H04B1/7117 ,  H04B1/712

Abstract: An apparatus and method for generating reference timings. Each of at least two Node Bs transmits a first channel signal for providing a reference timing and a second channel signal different from the first channel signal and a UE has a plurality of fingers for demodulating the first channel signals. A first timing generator receives an SFN of a reference Node B having a communication link established with the UE, selects a first channel FB timing from a reference finger, and generates an SFN reference timing based on the SFN and the selected first channel FB timing. A second timing generator generates a second channel FB timing to demodulate the second channel signal of the reference Node B from the selected first channel FB timing through offset control. A third timing generator generates an uplink channel FB timing having a predetermined offset from the second channel FB timing.

Abstract translation: 一种用于产生参考定时的装置和方法。 至少两个节点B中的每一个发送用于提供参考定时的第一信道信号和不同于第一信道信号的第二信道信号，并且UE具有用于解调第一信道信号的多个指状物。 第一定时发生器接收具有与UE建立的通信链路的参考节点B的SFN，从参考手指选择第一信道FB定时，并基于SFN和所选择的第一信道FB定时产生SFN参考定时。 第二定时发生器产生第二通道FB定时，以通过偏移控制从所选择的第一通道FB定时解调参考节点B的第二通道信号。 第三定时发生器产生具有来自第二通道FB定时的预定偏移的上行链路信道FB定时。

公开(公告)号：US20020091900A1

公开(公告)日：2002-07-11

申请号：US09943895

申请日：2001-08-31

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Sung-Chul Han

IPC: G06F012/00 ,  G06F012/14 ,  G06F012/16

CPC classification number: H03M13/6569 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957

Abstract: An interleaver is disclosed for a turbo encoder in an UMTS. The interleaver includes a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; a controller for generating a control signal for controlling an operation of the system by receiving the operating condition from the register; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i), provided from the register according to the control signal generated by the controller; and a data storage for sequentially storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.

Abstract translation: 公开了一种用于UMTS中的turbo编码器的交织器。 交织器包括用于更新和注册用于设置交织器的操作条件的多个参数的寄存器; 控制器，用于通过从所述寄存器接收所述操作条件来产生用于控制所述系统的操作的控制信号; 地址计算器，用于使用行间置换模式T（j），行内置换模式增量排列值incr（j）和行内置换基本序列s（i）来生成最终交错地址， 根据控制器产生的控制信号进行寄存; 以及数据存储器，用于顺序地存储输入到turbo编码器的数据，并输出与由地址计算器产生的地址相对应的数据。