公开(公告)号：US3778606A

公开(公告)日：1973-12-11

申请号：US3778606D

申请日：1972-02-23

Applicant: SANDERS ASSOCIATES INC

Inventor： SCHMITT J ,  STARKEY D

IPC: G06F17/14 ,  G06F15/34

CPC classification number: G06F17/141

Abstract: A method and apparatus for continually producing updated Fourier coefficient values of an input signal during each sample time. The Fourier coefficient F(k Omega ) is first calculated for any sequence of N samples of the input signal f(zT). To calculate the Fourier coefficients for the next ensuing sample time, the previously calculated Fourier coefficient value is updated by the addition of the product of the reference value and the difference between the new sample and the sample which occurred N samples earlier in time. This process is continued for each new sample.

Abstract translation: 一种用于在每个采样时间内不断产生输入信号的更新的傅里叶系数值的方法和装置。 首先对输入信号f（zT）的N个样本的任何序列计算傅立叶系数F（k OMEGA）。 为了计算下一个随后的采样时间的傅立叶系数，先前计算的傅立叶系数值通过加上参考值的乘积和新样本与在时间上较早发生的N个样本的样本之间的差异来更新。 每个新样本都继续进行此过程。

公开(公告)号：US3716843A

公开(公告)日：1973-02-13

申请号：US3716843D

申请日：1971-12-08

Applicant: SANDERS ASSOCIATES INC

Inventor： SCHMITT J ,  STARKEY D

IPC: G06F1/03 ,  G06F7/00 ,  G06F7/57 ,  H03B21/02 ,  G06F15/16

CPC classification number: G06F7/00 ,  G06F1/0328 ,  H03B21/025

Abstract: A modular signal processor which is assembled from a set of modules which have common input and output timing specifications such that any one module can be interconnected with any other module to perform a desired signal processing operation under the control of a timing generator. The timing generator is arranged to produce a clock signal of relatively high frequency and sequences of timing signals at a relatively lower frequency. Data is loaded into a module in response to a first one of the timing signal. The module then performs its operation or function upon the data to provide a result data. The result data is then read from the module in response to a subsequently occurring timing signal which is also employed to load the result data into another module. Specifically disclosed herein is a frequency synthesizer processor which employs the following modules: binary coded decimal to binary converter, phase accumulator, look up table and a digital to analog converter and filter.

Abstract translation: 一种模块化信号处理器，其由具有公共输入和输出定时规范的一组模块组装，使得任何一个模块可以与任何其他模块互连，以在定时发生器的控制下执行期望的信号处理操作。 定时发生器被布置成产生相对较高频率的时钟信号和相对较低频率的定时信号序列。 响应于定时信号中的第一个，将数据加载到模块中。 该模块然后对数据执行其操作或功能以提供结果数据。 然后响应于随后发生的定时信号从模块读取结果数据，其也用于将结果数据加载到另一模块中。 本文具体公开的是采用以下模块的频率合成器处理器：二进制编码的十进制到二进制转换器，相位累加器，查找表和数模转换器和滤波器。

公开(公告)号：US3758870A

公开(公告)日：1973-09-11

申请号：US3758870D

申请日：1972-02-23

Applicant: SANDERS ASSOCIATES INC

Inventor： SCHMITT J ,  MOSAKOWSKI J ,  STARKEY D

IPC: H04L27/18 ,  H04L27/233 ,  H04L27/22

CPC classification number: H04L27/2338

Abstract: A digital data demodulator for detecting binary information which is encoded upon an amplitude modulated or a phase modulated carrier wave. A specific example is presented for both a straight four phase and a modified four phase differentially coherent phase shift keyed (DCPSK) signal. The exemplary four phase DCPSK demodulator employs a discrete Fourier transform filter which provides updated Fourier coefficient values I + jQ during each sample interval. The I and Q values are rotated by 45* to form I'' and Q'' values. A synchronization network, a phase lock network and a data decoding network respond to the I, Q, I'' and Q'' values to synchronize the digital data demodulator with a received DCPSK signal and to decode the binary information encoded therein.

Abstract translation: 一种用于检测在幅度调制或相位调制载波上编码的二进制信息的数字数据解调器。 给出了直四相和修正的四相差分相干相移键控（DCPSK）信号的具体示例。 示例性四相DCPSK解调器采用离散傅里叶变换滤波器，其在每个采样间隔期间提供更新的傅里叶系数值I + jQ。 I和Q值旋转45°，形成I'和Q'值。 同步网络，锁相网络和数据解码网络对I，Q，I'和Q'值进行响应，以使数字数据解调器与接收到的DCPSK信号同步，并对其中编码的二进制信息进行解码。