公开(公告)号：US20210149593A1

公开(公告)日：2021-05-20

申请号：US16687086

申请日：2019-11-18

Applicant: SanDisk Technologies, LLC

Inventor： Vijay Chinchole

IPC: G06F3/06

Abstract: A data storage system includes a storage controller and a storage medium in communication with the storage controller. The storage medium includes a memory core comprising an array of memory cells and core control logic configured to perform operations on memory cells in the array in accordance with instructions received from the storage controller. The core control logic comprises a firmware-implemented condition evaluation machine configured to determine whether a plurality of memory core conditions are met. The core control logic also comprises a firmware-implemented signal setting machine configured to set or reset a plurality of respective memory operation signals to implement the operations on the memory cells based on respective condition evaluation machine determinations.

公开(公告)号：US20210141730A1

公开(公告)日：2021-05-13

申请号：US16682183

申请日：2019-11-13

Applicant: SanDisk Technologies, LLC

Inventor： Vijay Chinchole

IPC: G06F12/0862 ,  G06F3/06

Abstract: A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

公开(公告)号：US20190354369A1

公开(公告)日：2019-11-21

申请号：US15979627

申请日：2018-05-15

Applicant: SANDISK TECHNOLOGIES, LLC

Inventor： Vijay Chinchole ,  Vinayak Ghatawade ,  Naman Rastogi

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/16

Abstract: This disclosure provides techniques for debugging a computing system in a post-silicon validation process. In one example, a system can include a memory storing a set of instructions. The system can include a controller configured to fetch and execute the set of instructions. The system can include a logic block. The system can include a control bus coupling the memory, the controller, and the logic block. The control bus can include a first break-in circuit and a second break-in circuit each coupled to the controller. The first break-in circuit and the second break-in circuit can be configured to selectively cascade a break point from the controller through the logic block to halt execution of the set of instructions.

公开(公告)号：US20180357123A1

公开(公告)日：2018-12-13

申请号：US15934565

申请日：2018-03-23

Applicant: SanDisk Technologies LLC

Inventor： Yibo Yin ,  Henry Zhang ,  Po-Shen Lai ,  Vijay Chinchole ,  Spyridon Georgakis ,  Yan Li ,  Hiroyuki Mizukoshi ,  Toru Miwa ,  Jayesh Pakhale ,  Tz-Yi Liu

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1064

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

公开(公告)号：US11487548B2

公开(公告)日：2022-11-01

申请号：US16695759

申请日：2019-11-26

Applicant: SanDisk Technologies LLC

Inventor： Vijay Chinchole ,  Nisha Padattil Kuliyampattil ,  Sonam Agarwal ,  Akash Agarwal ,  Pavithra Devaraj ,  Yan Li

IPC: G11C7/00 ,  G06F9/38 ,  G06F9/34 ,  G06F12/02 ,  G06F9/54 ,  G06F11/30 ,  G06F9/22 ,  G06F3/06

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

公开(公告)号：US20210157607A1

公开(公告)日：2021-05-27

申请号：US16695759

申请日：2019-11-26

Applicant: SanDisk Technologies LLC

Inventor： Vijay Chinchole ,  Nisha Padattil Kuliyampattil ,  Sonam Agarwal ,  Akash Agarwal ,  Pavithra Devaraj ,  Yan Li

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/22 ,  G06F9/54 ,  G06F11/30 ,  G06F12/02

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.