公开(公告)号：US20230044232A1

公开(公告)日：2023-02-09

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Yuki MIZUTANI ,  Hisakazu OTOI ,  Masaaki HIGASHITANI ,  Hiroyuki OAGAWA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/48 ,  G11C8/14

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.