公开(公告)号：US20190051703A1

公开(公告)日：2019-02-14

申请号：US15672929

申请日：2017-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun SEL ,  Hisakazu OTOI ,  Seje TAKAKI ,  Tuan PHAM

IPC: H01L27/24 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423

Abstract: A two-dimensional array of vertical field effect transistors is provided, which includes a one-dimensional array of ladder-shaped gate electrode lines. Each of the ladder-shaped gate electrode lines includes a pair of rail portions that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction and rung portions extending between the pair of rail portions along the second horizontal direction. The vertical field effect transistors include gate dielectrics located in each opening defined by a neighboring pair of rung portions, and vertical semiconductor channels laterally surrounded by a respective one of the gate dielectrics and extending along a vertical direction. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines of a three-dimensional ReRAM device.

公开(公告)号：US20240260266A1

公开(公告)日：2024-08-01

申请号：US18356896

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Takashi KASHIMURA ,  Tomohiro KUBO ,  Hisakazu OTOI ,  Hiroyuki TANAKA ,  Takumi MORIYAMA ,  Ryota SUZUKI

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

公开(公告)号：US20240172431A1

公开(公告)日：2024-05-23

申请号：US18425996

申请日：2024-01-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Lito De La RAMA ,  Masaaki HIGASHITANI ,  Koichi MATSUNO ,  Marika GUNJI-YONEOKA ,  Makoto KOTO ,  Hisakazu OTOI ,  Masanori TSUTSUMI

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/06 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

公开(公告)号：US20200312863A1

公开(公告)日：2020-10-01

申请号：US16366245

申请日：2019-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Yoshitaka OTSU ,  Hisakazu OTOI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

公开(公告)号：US20210384207A1

公开(公告)日：2021-12-09

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Junpei KANAZAWA ,  Hisakazu OTOI ,  Hironori MATSUOKA ,  Raiden MATSUNO

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

公开(公告)号：US20200312864A1

公开(公告)日：2020-10-01

申请号：US16366330

申请日：2019-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Yoshitaka OTSU ,  Hisakazu OTOI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

公开(公告)号：US20190386108A1

公开(公告)日：2019-12-19

申请号：US16009661

申请日：2018-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Hisakazu OTOI ,  Akio NISHIDA

IPC: H01L29/423 ,  H01L27/11556 ,  H01L29/66

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a tunneling dielectric layer, a vertical semiconductor channel, and a vertical stack of charge storage structures. Each of the charge storage structures includes an annular silicon nitride portion, a lower silicon nitride portion underlying the upper silicon nitride portion, and a spacer located between the upper silicon nitride portion and the lower silicon nitride portion. The upper and lower silicon nitride portions may be charge storage regions, while the spacer may be a floating gate or a dielectric spacer.

公开(公告)号：US20230044232A1

公开(公告)日：2023-02-09

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Yuki MIZUTANI ,  Hisakazu OTOI ,  Masaaki HIGASHITANI ,  Hiroyuki OAGAWA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/48 ,  G11C8/14

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20190252396A1

公开(公告)日：2019-08-15

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru MUSHIGA ,  Kenji SUGIURA ,  Hisakazu OTOI ,  Shigehisa INOUE ,  Yuki FUKUDA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/762

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/40114 ,  H01L29/40117

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

公开(公告)号：US20190103467A1

公开(公告)日：2019-04-04

申请号：US15720490

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seje TAKAKI ,  Jongsun SEL ,  Hisakazu OTOI ,  Chao Feng YEH

IPC: H01L29/417 ,  H01L27/02 ,  H01L27/11

Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.