公开(公告)号：US20240206171A1

公开(公告)日：2024-06-20

申请号：US18352025

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA ,  Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20240206169A1

公开(公告)日：2024-06-20

申请号：US18351992

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20240172431A1

公开(公告)日：2024-05-23

申请号：US18425996

申请日：2024-01-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Lito De La RAMA ,  Masaaki HIGASHITANI ,  Koichi MATSUNO ,  Marika GUNJI-YONEOKA ,  Makoto KOTO ,  Hisakazu OTOI ,  Masanori TSUTSUMI

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/06 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

公开(公告)号：US20230164988A1

公开(公告)日：2023-05-25

申请号：US17664550

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5226

Abstract: A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

公开(公告)号：US20220367487A1

公开(公告)日：2022-11-17

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng ZHANG ,  Yanli ZHANG ,  Xiang YANG ,  Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/1159 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/06 ,  H01L21/764

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20220208748A1

公开(公告)日：2022-06-30

申请号：US17134997

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Kwang-ho KIM

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.

公开(公告)号：US20200235120A1

公开(公告)日：2020-07-23

申请号：US16251863

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Fumiaki TOYAMA ,  Johann ALSMEIER ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

Abstract: An alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the alternating stack. Backside trenches, a moat trench, and a contact opening are formed through the alternating stack, and are subsequently filled with sacrificial backside trench fill material structures, a sacrificial moat trench fill structure, and a sacrificial contact opening fill structure, respectively. The sacrificial moat trench fill structure is replaced with tubular dielectric wall structure. Portions of the dielectric spacer layers located outside the tubular dielectric wall structure are replaced with electrically conductive layers. The sacrificial backside trench fill material structures are replaced with backside trench fill structures. The sacrificial contact opening fill structure is replaced with a conductive via structure. Concurrent formation of the backside trenches, the moat trench, and the contact opening reduces processing steps and cost.

公开(公告)号：US20230363162A1

公开(公告)日：2023-11-09

申请号：US18158783

申请日：2023-01-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L23/5226 ,  H01L23/5283

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory film located in the memory opening, and a composite metal oxide semiconductor channel containing a first semiconducting metal oxide channel layer having a first band gap and a second semiconducting metal oxide channel layer having a second band gap that is different from the first band gap.

公开(公告)号：US20230008286A1

公开(公告)日：2023-01-12

申请号：US17370317

申请日：2021-07-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L23/00

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

公开(公告)号：US20220310655A1

公开(公告)日：2022-09-29

申请号：US17215312

申请日：2021-03-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a gate dielectric and a ferroelectric semiconductor channel layer that is laterally spaced from the electrically conductive layers by the gate dielectric.