公开(公告)号：US10347647B1

公开(公告)日：2019-07-09

申请号：US15850073

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Keisuke Shigemura ,  Junichi Ariyoshi ,  Kazuki Kajitani ,  Yuji Fukano

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/265 ,  H01L21/266 ,  H01L27/11524 ,  H01L29/40

Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.